Developments in integrated circuit technology have focused on improving the integration density of various electronic components (e.g., transistors, capacitors, diodes, resistors, inductors, etc.) into a given chip or wafer area. Various improvements have involved the reduction of minimum component size, permitting more components to be integrated on the semiconductor die or wafer. Such two dimensional (2D) integration density improvements are physically limited by aspect ratios of devices, dimensions of dies, design rules of technology nodes, etc.
Three dimensional integrated circuits (3DIC) are used to resolve some of the limitations of 2D integrated circuits. Plural dies are stacked vertically within a single package and electrically connected to each other. Through substrate vias (TSVs) are often used in stacked wafer/die packaging structures to connect the wafers or dies. TSVs are vertical openings passing completely though semiconductor substrates and filled with conductive material to provide connections between stacked wafers or dies. The total interconnect length of the integrated circuits in 3DIC is decreased compared to corresponding ones in 2D integrated circuit.